https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86802
Jim Wilson <wilson at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |NEW
Last reconfirmed| |2018-08-01
Assignee|unassigned at gcc dot gnu.org |wilson at gcc dot
gnu.org
Ever confirmed|0 |1
--- Comment #1 from Jim Wilson <wilson at gcc dot gnu.org> ---
There is no known shipping RISC-V hardware at this time that has speculation
support.
However, we do expect that we will have such hardware in the future. An
informal request has been made to add an architecturally defined instruction
sequence that can be used as a speculation barrier. Perhaps one of the hints
can be used for this, or maybe one of the uncompressed nop effect instructions
can be used. The PPC uses ori instructions for instance, or'ing a 0 into a
register. This discussion is likely to take some months.
Meanwhile, we can just say that no speculation barriers are required.
