[Bug rtl-optimization/84660] Combine doing wrong optimization for 64 bits with SHIFT_COUNT_TRUNCATED target

[wilson at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84660

--- Comment #8 from Jim Wilson <wilson at gcc dot gnu.org> ---
Author: wilson
Date: Mon Apr  2 22:37:21 2018
New Revision: 259019

URL: https://gcc.gnu.org/viewcvs?rev=259019&root=gcc&view=rev
Log:
RISC-V: Fix for combine bug with shift and AND operations.

        PR rtl-optimization/84660
        gcc/
        * config/riscv/riscv.h (SHIFT_COUNT_TRUNCATED): Set to zero.
        * config/riscv/riscv.md (<optab>si3): Use QImode shift count.
        (<optab>di3, <optab>si3_extend): Likewise.
        (<optab>si3_mask, <optab>si3_mask_1): New.
        (<optab>di3_mask, <optab>di3_mask_1): New.
        (<optab>si3_extend_mask, <optab>si3_extend_mask_1): New.
        (lshrsi3_zero_extend_1): Use VOIDmode shift count.
        * config/riscv/sync.md (atomic_test_and_set): Emit QImode shift count.
        gcc/testsuite/
        * gcc.target/riscv/pr84660.c: New.
        * gcc.target/riscv/shift-and-1.c: New.
        * gcc.target/riscv/shift-and-2.c: New.

Added:
    trunk/gcc/testsuite/gcc.target/riscv/pr84660.c
    trunk/gcc/testsuite/gcc.target/riscv/shift-and-1.c
    trunk/gcc/testsuite/gcc.target/riscv/shift-and-2.c
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/riscv/riscv.h
    trunk/gcc/config/riscv/riscv.md
    trunk/gcc/config/riscv/sync.md
    trunk/gcc/testsuite/ChangeLog