https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84878
--- Comment #2 from Peter Bergner <bergner at gcc dot gnu.org> ---
So we segv in ddg.c:add_cross_iteration_register_deps() at this code:
/* Create inter-loop true dependences and anti dependences. */
for (r_use = DF_REF_CHAIN (last_def); r_use != NULL; r_use = r_use->next)
{
rtx_insn *use_insn = DF_REF_INSN (r_use->ref);
^^^^ segv's
We currently have:
(gdb) pr def_insn
(insn 331 321 332 12 (parallel [
(set (reg:V4SI 239 [ vect__4.11 ])
(unspec:V4SI [
(reg:V4SF 134 [ vect_cst__39 ])
(const_int 0 [0])
] UNSPEC_VCTSXS))
(set (reg:SI 110 vscr)
(unspec:SI [
(const_int 0 [0])
] UNSPEC_SET_VSCR))
]) "bug.i":9 1812 {altivec_vctsxs}
(expr_list:REG_UNUSED (reg:V4SI 239 [ vect__4.11 ])
(nil)))
(gdb) p DF_REF_REGNO (last_def)
$4 = 110
So we're looking at the definition of the VSCR hard register, which is a global
register (ie, global_regs[110] == 1), but there are no following explicit uses
of the VSCR reg, so:
(gdb) p DF_REF_INSN_INFO(r_use->ref)
$5 = (df_insn_info *) 0x0
When we call DF_REF_INSN(r_use->ref) which deferences
DF_REF_INSN_INFO(r_use->ref), we segv.
The following patch cures the segv:
Index: gcc/ddg.c
===================================================================
--- gcc/ddg.c (revision 258802)
+++ gcc/ddg.c (working copy)
@@ -295,6 +295,11 @@ add_cross_iteration_register_deps (ddg_p
/* Create inter-loop true dependences and anti dependences. */
for (r_use = DF_REF_CHAIN (last_def); r_use != NULL; r_use = r_use->next)
{
+ /* PR84878: Some definitions of global hard registers may not have
+ any following uses or they may be artificial, so skip them. */
+ if (DF_REF_INSN_INFO (r_use->ref) == NULL)
+ continue;
+
rtx_insn *use_insn = DF_REF_INSN (r_use->ref);
if (BLOCK_FOR_INSN (use_insn) != g->bb)
