[Bug rtl-optimization/84123] internal compiler error: in gen_rtx_SUBREG, at emit-rtl.c:908, alpha linux.

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84123

Uroš Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2018-01-30
                 CC|                            |segher at gcc dot gnu.org
     Ever confirmed|0                           |1

--- Comment #1 from Uroš Bizjak <ubizjak at gmail dot com> ---
Combine pass is trying to simplify:

(insn 13 12 16 2 (set (reg:SI 141 [ ID ])
        (zero_extend:SI (subreg:QI (reg:DI 48 $f16 [ ID ]) 0))) 48
{zero_extendqisi2}

via change_zero_ext (combine.c):

11486         else if (GET_CODE (x) == ZERO_EXTEND
11487                  && GET_CODE (XEXP (x, 0)) == SUBREG
11488                  && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x,
0))))
11489                  && !paradoxical_subreg_p (XEXP (x, 0))
11490                  && subreg_lowpart_p (XEXP (x, 0)))
11491           {
11492             inner_mode = as_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)));
11493             size = GET_MODE_PRECISION (inner_mode);
11494             x = SUBREG_REG (XEXP (x, 0));
(gdb) 
11495             if (GET_MODE (x) != mode)
11496               x = gen_lowpart_SUBREG (mode, x);
11497           }

This won't work when x in line 11496 is a hard register and mode is unsupported
with targetm.hard_regno_mode_ok.

(gdb) p debug_rtx (x)
(reg:DI 48 $f16 [ ID ])
$1 = void
(gdb) p mode
$2 = {m_mode = E_SImode}

(which in case of alpha is defined as:

--cut here--
/* Implement TARGET_HARD_REGNO_MODE_OK.  On Alpha, the integer registers
   can hold any mode.  The floating-point registers can hold 64-bit
   integers as well, but not smaller values.  */

static bool
alpha_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
  if (IN_RANGE (regno, 32, 62))
    return (mode == SFmode
            || mode == DFmode
            || mode == DImode
            || mode == SCmode
            || mode == DCmode);
  return true;
}
--cut here--

We should skip RTXes that will result in certain ICE here, so:

--cut here--
diff --git a/gcc/combine.c b/gcc/combine.c
index 6adc0a7d6f8..05ad18bff89 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -11493,7 +11493,13 @@ change_zero_ext (rtx pat)
          size = GET_MODE_PRECISION (inner_mode);
          x = SUBREG_REG (XEXP (x, 0));
          if (GET_MODE (x) != mode)
-           x = gen_lowpart_SUBREG (mode, x);
+           {
+             if (HARD_REGISTER_P (x)
+                 && !can_change_dest_mode (x, 0, mode))
+               continue;
+
+             x = gen_lowpart_SUBREG (mode, x);
+           }
        }
       else if (GET_CODE (x) == ZERO_EXTEND
               && REG_P (XEXP (x, 0))
--cut here--