https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83862
Michael Meissner <meissner at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |ASSIGNED
Last reconfirmed| |2018-01-16
Assignee|unassigned at gcc dot gnu.org |meissner at gcc dot
gnu.org
Ever confirmed|0 |1
--- Comment #1 from Michael Meissner <meissner at gcc dot gnu.org> ---
The issue is signbit for 128-bit floating point types wants to optimize signbit
coming from memory to load the high 64-bit value directly into the GPR, and
then do an unsigned shift left of 63 bits to isolate the sign bit.
However, if the floating point value is IEEE 128-bit, the system is little
endian, and the address is indexed (register+register), the optimization will
fail because the compiler will generate an address of the form:
(set (reg:DF <gpr>)
(mem:DF (plus:DI (plus:DI (reg:DI <base>)
(reg:DI <index>))
(const_int 8))))
For little endian systems, we would need a temporary register to put the sum of
the base + index registers, and then we can do a load <tmp reg>+8.
