[Bug target/83467] [7/8 Regression] ICE: in assign_by_spills, at lra-assigns.c:1476: unable to find a register to spill with -flive-range-shrinkage -m8bit-idiv

[uros at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83467

--- Comment #4 from uros at gcc dot gnu.org ---
Author: uros
Date: Thu Dec 21 19:00:28 2017
New Revision: 255949

URL: https://gcc.gnu.org/viewcvs?rev=255949&root=gcc&view=rev
Log:
        PR target/83467
        * config/i386/i386.md (*ashl<mode>3_mask): Add operand
        constraints to operand 2.
        (*ashl<mode>3_mask_1): Ditto.
        (*<shift_insn><mode>3_mask): Ditto.
        (*<shift_insn><mode>3_mask_1): Ditto.
        (*<rotate_insn><mode>3_mask): Ditto.
        (*<rotate_insn><mode>3_mask_1): Ditto.

testsuite/ChangeLog:

        PR target/83467
        * gcc.target/i386/pr83467-1.c: New test.
        * gcc.target/i386/pr83467-2.c: Ditto.


Added:
    trunk/gcc/testsuite/gcc.target/i386/pr83467-1.c
    trunk/gcc/testsuite/gcc.target/i386/pr83467-2.c
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/i386/i386.md
    trunk/gcc/testsuite/ChangeLog