https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83399
Bug ID: 83399
Summary: Power8 ICE During LRA with 2-op rtl pattern for lvx
instruction
Product: gcc
Version: unknown
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: kelvin at gcc dot gnu.org
Target Milestone: ---
Created attachment 42855
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=42855&action=edit
Preprocessed source code to reproduce problem.
During lra_eliminate (0, 1), gcc attempts to eliminate the sfp (frame pointer)
register by replacing all uses of sfp with the sp (stack pointer) register and
an adjusted offset.
In the case that the rtl (before lra_eliminate) matches the pattern for
altivec_lvx_<mode>_2op, shown below:
(define_insn "altivec_lvx_<mode>_2op"
[(set (match_operand:VM2 0 "register_operand" "=v")
(mem:VM2 (and:DI (plus:DI (match_operand:DI 1 "register_operand" "b")
(match_operand:DI 2 "register_operand" "r"))
(const_int -16))))]
"TARGET_ALTIVEC && TARGET_64BIT"
"lvx %0,%1,%2"
[(set_attr "type" "vecload")])
with op1 represented by (reg/f:DI 111 sfp) the (stack frame pointer),
lra_eliminate_regs_1 replaces op1 with
(plus:DI (reg/f:DI 111 sfp) (const_int -160))
I believe the intent is to ultimately eliminate sfp and replace it with sp,
which is offset by the size of the activation frame (160 bytes).
After transforming the rtl code as described, there is no insn pattern to match
the revised rtl, resulting in an ICE.
Compiling with "gcc -O3 -S" options ends with the following error messages:
At top of rs6000_override_internal, global_init: 1
TARGET_DEFAULT = 0x1f07e05c09613f: -maltivec, -mcmpb,
-mcrypto, -mdirect-move, -mno-dlmzb, \
-mefficient-unaligned-vsx,
-mno-float128, -mno-float128-type, \
-mno-float128-hardware,
-mfprnd, -mhard-dfp, -mhtm, -mno-isel, \
-mmfcrf, -mno-mfpgpr,
-mno-modulo, -mno-mulhw, -mno-multiple, \
-mpopcntb, -mpopcntd,
-mpower8-fusion, -mno-power8-fusion-sign, \
-mpower8-vector,
-mno-power9-dform-scalar, \
-mno-power9-dform-vector,
-mno-power9-fusion, -mno-power9-minmax, \
-mno-power9-misc,
-mno-power9-vector, -mpowerpc-gfxopt, \
-mpowerpc-gpopt,
-mquad-memory, -mquad-memory-atomic, \
-mrecip-precision,
-mno-save-toc-indirect, -mno-string, \
-mno-toc-fusion, -mupdate,
-mupper-regs-di, -mupper-regs-df, \
-mupper-regs-sf, -mvsx,
-mvsx-small-integer, -mno-vsx-timode, -m64, \
-m32, -mno-eabi, -mlittle,
-mbig, -mno-relocatable, \
-mno-strict-align,
-mno-soft-float, -mno-string
x_rs6000_isa_flags = <none>
rs6000_isa_flags_explicit = <none>
rs6000_isa_flags = 0x1f07e05c09613f: -maltivec, -mcmpb,
-mcrypto, -mdirect-move, -mno-dlmzb, \
-mefficient-unaligned-vsx,
-mno-float128, -mno-float128-type, \
-mno-float128-hardware,
-mfprnd, -mhard-dfp, -mhtm, -mno-isel, \
-mmfcrf, -mno-mfpgpr,
-mno-modulo, -mno-mulhw, -mno-multiple, \
-mpopcntb, -mpopcntd,
-mpower8-fusion, -mno-power8-fusion-sign, \
-mpower8-vector,
-mno-power9-dform-scalar, \
-mno-power9-dform-vector,
-mno-power9-fusion, -mno-power9-minmax, \
-mno-power9-misc,
-mno-power9-vector, -mpowerpc-gfxopt, \
-mpowerpc-gpopt,
-mquad-memory, -mquad-memory-atomic, \
-mrecip-precision,
-mno-save-toc-indirect, -mno-string, \
-mno-toc-fusion, -mupdate,
-mupper-regs-di, -mupper-regs-df, \
-mupper-regs-sf, -mvsx,
-mvsx-small-integer, -mno-vsx-timode, -m64, \
-m32, -mno-eabi, -mlittle,
-mbig, -mno-relocatable, \
-mno-strict-align,
-mno-soft-float, -mno-string
set_masks is POWERPC_MASKS
set_masks = 0x3fa7ffdedffb7a: -maltivec, -mcmpb,
-mcrypto, -mdirect-move, -mdlmzb, \
-mefficient-unaligned-vsx,
-mfloat128, -mfloat128-type, \
-mfloat128-hardware,
-mfprnd, -mhard-dfp, -mhtm, -misel, -mmfcrf, \
-mmfpgpr, -mmodulo,
-mmulhw, -mno-multiple, -mpopcntb, -mpopcntd, \
-mpower8-fusion,
-mno-power8-fusion-sign, -mpower8-vector, \
-mpower9-dform-scalar,
-mpower9-dform-vector, -mpower9-fusion, \
-mpower9-minmax,
-mpower9-misc, -mpower9-vector, -mpowerpc-gfxopt, \
-mpowerpc-gpopt,
-mquad-memory, -mquad-memory-atomic, \
-mrecip-precision,
-mno-save-toc-indirect, -mno-string, \
-mtoc-fusion, -mno-update,
-mupper-regs-di, -mupper-regs-df, \
-mupper-regs-sf, -mvsx,
-mvsx-small-integer, -mvsx-timode, -mno-64, \
-m32, -mno-eabi,
-mno-little, -mbig, -mno-relocatable, \
-mstrict-align,
-msoft-float, -mno-string
Before adjusting set_masks
set_masks = 0x3fa7ffdedffb7a: -maltivec, -mcmpb,
-mcrypto, -mdirect-move, -mdlmzb, \
-mefficient-unaligned-vsx,
-mfloat128, -mfloat128-type, \
-mfloat128-hardware,
-mfprnd, -mhard-dfp, -mhtm, -misel, -mmfcrf, \
-mmfpgpr, -mmodulo,
-mmulhw, -mno-multiple, -mpopcntb, -mpopcntd, \
-mpower8-fusion,
-mno-power8-fusion-sign, -mpower8-vector, \
-mpower9-dform-scalar,
-mpower9-dform-vector, -mpower9-fusion, \
-mpower9-minmax,
-mpower9-misc, -mpower9-vector, -mpowerpc-gfxopt, \
-mpowerpc-gpopt,
-mquad-memory, -mquad-memory-atomic, \
-mrecip-precision,
-mno-save-toc-indirect, -mno-string, \
-mtoc-fusion, -mno-update,
-mupper-regs-di, -mupper-regs-df, \
-mupper-regs-sf, -mvsx,
-mvsx-small-integer, -mvsx-timode, -mno-64, \
-m32, -mno-eabi,
-mno-little, -mbig, -mno-relocatable, \
-mstrict-align,
-msoft-float, -mno-string
rs6000_isa_flags_explicit = <none>
After taking care of set_masks:
set_masks = 0x3fa7ffdedffb7a: -maltivec, -mcmpb,
-mcrypto, -mdirect-move, -mdlmzb, \
-mefficient-unaligned-vsx,
-mfloat128, -mfloat128-type, \
-mfloat128-hardware,
-mfprnd, -mhard-dfp, -mhtm, -misel, -mmfcrf, \
-mmfpgpr, -mmodulo,
-mmulhw, -mno-multiple, -mpopcntb, -mpopcntd, \
-mpower8-fusion,
-mno-power8-fusion-sign, -mpower8-vector, \
-mpower9-dform-scalar,
-mpower9-dform-vector, -mpower9-fusion, \
-mpower9-minmax,
-mpower9-misc, -mpower9-vector, -mpowerpc-gfxopt, \
-mpowerpc-gpopt,
-mquad-memory, -mquad-memory-atomic, \
-mrecip-precision,
-mno-save-toc-indirect, -mno-string, \
-mtoc-fusion, -mno-update,
-mupper-regs-di, -mupper-regs-df, \
-mupper-regs-sf, -mvsx,
-mvsx-small-integer, -mvsx-timode, -mno-64, \
-m32, -mno-eabi,
-mno-little, -mbig, -mno-relocatable, \
-mstrict-align,
-msoft-float, -mno-string
Before checking have_cpu
rs6000_isa_flags = 0x1f07e05c09613f: -maltivec, -mcmpb,
-mcrypto, -mdirect-move, -mno-dlmzb, \
-mefficient-unaligned-vsx,
-mno-float128, -mno-float128-type, \
-mno-float128-hardware,
-mfprnd, -mhard-dfp, -mhtm, -mno-isel, \
-mmfcrf, -mno-mfpgpr,
-mno-modulo, -mno-mulhw, -mno-multiple, \
-mpopcntb, -mpopcntd,
-mpower8-fusion, -mno-power8-fusion-sign, \
-mpower8-vector,
-mno-power9-dform-scalar, \
-mno-power9-dform-vector,
-mno-power9-fusion, -mno-power9-minmax, \
-mno-power9-misc,
-mno-power9-vector, -mpowerpc-gfxopt, \
-mpowerpc-gpopt,
-mquad-memory, -mquad-memory-atomic, \
-mrecip-precision,
-mno-save-toc-indirect, -mno-string, \
-mno-toc-fusion, -mupdate,
-mupper-regs-di, -mupper-regs-df, \
-mupper-regs-sf, -mvsx,
-mvsx-small-integer, -mno-vsx-timode, -m64, \
-m32, -mno-eabi, -mlittle,
-mbig, -mno-relocatable, \
-mno-strict-align,
-mno-soft-float, -mno-string
Since we have_cpu, we mask off set_masks bits
rs6000_isa_flags = 0x000000000005: -mno-altivec, -mno-cmpb,
-mno-crypto, -mno-direct-move, -mno-dlmzb, \
-mno-efficient-unaligned-vsx,
-mno-float128, -mno-float128-type, \
-mno-float128-hardware,
-mno-fprnd, -mno-hard-dfp, -mno-htm, \
-mno-isel, -mno-mfcrf,
-mno-mfpgpr, -mno-modulo, -mno-mulhw, \
-mno-multiple, -mno-popcntb,
-mno-popcntd, -mno-power8-fusion, \
-mno-power8-fusion-sign,
-mno-power8-vector, \
-mno-power9-dform-scalar,
-mno-power9-dform-vector, \
-mno-power9-fusion,
-mno-power9-minmax, -mno-power9-misc, \
-mno-power9-vector,
-mno-powerpc-gfxopt, -mno-powerpc-gpopt, \
-mno-quad-memory,
-mno-quad-memory-atomic, -mno-recip-precision, \
-mno-save-toc-indirect,
-mno-string, -mno-toc-fusion, -mupdate, \
-mno-upper-regs-di,
-mno-upper-regs-df, -mno-upper-regs-sf, -mno-vsx, \
-mno-vsx-small-integer,
-mno-vsx-timode, -m64, -m32, -mno-eabi, \
-mlittle, -mbig,
-mno-relocatable, -mno-strict-align, \
-mno-soft-float, -mno-string
After setting flags to [cpu_index].target_enable
rs6000_isa_flags = 0x1f07e05c09613f: -maltivec, -mcmpb,
-mcrypto, -mdirect-move, -mno-dlmzb, \
-mefficient-unaligned-vsx,
-mno-float128, -mno-float128-type, \
-mno-float128-hardware,
-mfprnd, -mhard-dfp, -mhtm, -mno-isel, \
-mmfcrf, -mno-mfpgpr,
-mno-modulo, -mno-mulhw, -mno-multiple, \
-mpopcntb, -mpopcntd,
-mpower8-fusion, -mno-power8-fusion-sign, \
-mpower8-vector,
-mno-power9-dform-scalar, \
-mno-power9-dform-vector,
-mno-power9-fusion, -mno-power9-minmax, \
-mno-power9-misc,
-mno-power9-vector, -mpowerpc-gfxopt, \
-mpowerpc-gpopt,
-mquad-memory, -mquad-memory-atomic, \
-mrecip-precision,
-mno-save-toc-indirect, -mno-string, \
-mno-toc-fusion, -mupdate,
-mupper-regs-di, -mupper-regs-df, \
-mupper-regs-sf, -mvsx,
-mvsx-small-integer, -mno-vsx-timode, -m64, \
-m32, -mno-eabi, -mlittle,
-mbig, -mno-relocatable, \
-mno-strict-align,
-mno-soft-float, -mno-string
Before defaults, rs6000_isa_flags= 0x1f07e05c09613f: -maltivec, -mcmpb,
-mcrypto, -mdirect-move, -mno-dlmzb, \
-mefficient-unaligned-vsx,
-mno-float128, -mno-float128-type, \
-mno-float128-hardware,
-mfprnd, -mhard-dfp, -mhtm, -mno-isel, \
-mmfcrf, -mno-mfpgpr,
-mno-modulo, -mno-mulhw, -mno-multiple, \
-mpopcntb, -mpopcntd,
-mpower8-fusion, -mno-power8-fusion-sign, \
-mpower8-vector,
-mno-power9-dform-scalar, \
-mno-power9-dform-vector,
-mno-power9-fusion, -mno-power9-minmax, \
-mno-power9-misc,
-mno-power9-vector, -mpowerpc-gfxopt, \
-mpowerpc-gpopt,
-mquad-memory, -mquad-memory-atomic, \
-mrecip-precision,
-mno-save-toc-indirect, -mno-string, \
-mno-toc-fusion, -mupdate,
-mupper-regs-di, -mupper-regs-df, \
-mupper-regs-sf, -mvsx,
-mvsx-small-integer, -mno-vsx-timode, \
-m64, -m32, -mno-eabi,
-mlittle, -mbig, -mno-relocatable, \
-mno-strict-align,
-mno-soft-float, -mno-string
At bottom of rs6000_override_internal
x_rs6000_isa_flags = <none>
rs6000_isa_flags_explicit = <none>
rs6000_isa_flags = 0x3f06e07c0d713f: -maltivec, -mcmpb,
-mcrypto, -mdirect-move, -mno-dlmzb, \
-mefficient-unaligned-vsx,
-mno-float128, -mfloat128-type, \
-mno-float128-hardware,
-mfprnd, -mhard-dfp, -mhtm, -mno-isel, \
-mmfcrf, -mno-mfpgpr,
-mno-modulo, -mno-mulhw, -mno-multiple, \
-mpopcntb, -mpopcntd,
-mpower8-fusion, -mpower8-fusion-sign, \
-mpower8-vector,
-mno-power9-dform-scalar, \
-mno-power9-dform-vector,
-mno-power9-fusion, -mno-power9-minmax, \
-mno-power9-misc,
-mno-power9-vector, -mpowerpc-gfxopt, \
-mpowerpc-gpopt,
-mno-quad-memory, -mquad-memory-atomic, \
-mrecip-precision,
-mno-save-toc-indirect, -mno-string, \
-mno-toc-fusion, -mupdate,
-mupper-regs-di, -mupper-regs-df, \
-mupper-regs-sf, -mvsx,
-mvsx-small-integer, -mvsx-timode, -m64, \
-m32, -mno-eabi, -mlittle,
-mbig, -mno-relocatable, \
-mno-strict-align,
-mno-soft-float, -mno-string
builtin mask = 0x800204d01d013: altivec, vsx, no-spe,
no-paired, fre, fres, no-frsqrte, no-frsqrtes, \
popcntd, no-cell,
power8-vector, no-power9-vector, no-power9-misc, \
crypto, htm, hard-dfp,
hard-float, long-double-128, float128
headache.c: In function ‘foo’:
headache.c:21:1: internal compiler error: in lra_set_insn_recog_data, at
lra.c:978
}
^
0x10aac26b lra_set_insn_recog_data(rtx_insn*)
/home/kelvin/gcc-root/gcc-trunk/gcc/lra.c:976
0x10aa8f53 lra_get_insn_recog_data
/home/kelvin/gcc-root/gcc-trunk/gcc/lra-int.h:491
0x10aaeca3 lra_update_insn_regno_info(rtx_insn*)
/home/kelvin/gcc-root/gcc-trunk/gcc/lra.c:1603
0x10aaf703 lra_push_insn_1
/home/kelvin/gcc-root/gcc-trunk/gcc/lra.c:1755
0x10aaf767 lra_push_insn(rtx_insn*)
/home/kelvin/gcc-root/gcc-trunk/gcc/lra.c:1763
0x10aaf9c7 push_insns
/home/kelvin/gcc-root/gcc-trunk/gcc/lra.c:1806
0x10aafcfb lra_process_new_insns(rtx_insn*, rtx_insn*, rtx_insn*, char const*)
/home/kelvin/gcc-root/gcc-trunk/gcc/lra.c:1854
0x10ad195b curr_insn_transform
/home/kelvin/gcc-root/gcc-trunk/gcc/lra-constraints.c:4264
0x10ad3a07 lra_constraints(bool)
/home/kelvin/gcc-root/gcc-trunk/gcc/lra-constraints.c:4754
0x10ab1bdf lra(_IO_FILE*)
/home/kelvin/gcc-root/gcc-trunk/gcc/lra.c:2392
0x10a2c6eb do_reload
/home/kelvin/gcc-root/gcc-trunk/gcc/ira.c:5451
0x10a2cf1f execute
/home/kelvin/gcc-root/gcc-trunk/gcc/ira.c:5635
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
make: *** [problem-report.s] Error 1
