https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80510
Bug ID: 80510
Summary: Optimize Power7/power8 Altivec load/stores
Product: gcc
Version: 8.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: meissner at gcc dot gnu.org
Target Milestone: ---
In looking at PR target/68163, I noticed that if the register allocator wanted
to store a scalar value in a traditional Altivec register, it would generate
the following code:
Copy value from an Altivec register to a FPR register
Use a d-form (register+offset) store to store the value
This is true of DImode and DFmode stores from Altivec registers for ISA 2.06
(power7) and once the specific problem of PR 68163 is solved not to copy the
value to a GPR register, it will also be true of SFmode stores in ISA 2.07
(power8). It is not an issue for ISA 3.0, since that machine has D-form
stores, and it can generate the store directly.
The solution is to move the offset into a scratch register, and change the
memory operation from d-form to x-form. On power8, loading the offset is a
single cycle while XXLOR (DI/DF move) is 2 cycles, while XSCPSGNDP (SF move) is
6 cycles.
The bug can be solved with a define_peephole2, but it may be useful to see if
there is a way to get the register allocator to prefer generating the X-FORM
load (by moving the offset to a register) instead of generating a move and then
a store.
