https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80425
--- Comment #2 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
We have the following fragment:
8: r96:DI=zero_extend(r93:SI)
REG_DEAD r93:SI
13: r91:V8DI#0=r95:V16SI>>r96:DI
REG_DEAD r96:DI
REG_DEAD r95:V16SI
IRA allocates general regs to r96 and r93. And it means insn 8
alternative (0) r (1) rmWz {*zero_extendsidi2} as requiring no any
reload.
So why does IRA choose general regs for r96 instead of SSE ones. For insn 8 we
have the following alternatives:
"=...r ,...,?*Ym,..."
"... rmWz,...,r ,..."
Alternative '?*Ym, r' discourages usage of SSE regs as Y has *
(exluded from pseudo class consideration). It is also discouraged in
LRA as it has ?
So I don't know how to fix it in IRA or in LRA. I am pretty sure the
old RA and reload would have had the same problem.
Probably the issue should be fixed in machine dependent code. But the fix
might create more problems.
