https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79295
Michael Meissner <meissner at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |NEW
Last reconfirmed| |2017-02-01
Ever confirmed|0 |1
--- Comment #3 from Michael Meissner <meissner at gcc dot gnu.org> ---
The insn needs to have a "v" constraint, rather than "" which allows any
register. In addition in the PowerPC backend, we tend to want at least
gpc_reg_operand which can do extra checks, or altivec_register_operand which
will only match Altivec registers. The insn should look like:
(define_insn "bcd<bcd_add_sub>"
[(set (match_operand:V1TI 0 "gpc_reg_operand" "=v")
(unspec:V1TI [(match_operand:V1TI 1 "gpc_reg_operand" "v")
(match_operand:V1TI 2 "gpc_reg_operand" "v")
(match_operand:QI 3 "const_0_to_1_operand" "n")]
UNSPEC_BCD_ADD_SUB))
(clobber (reg:CCFP CR6_REGNO))]
"TARGET_P8_VECTOR"
"bcd<bcd_add_sub>. %0,%1,%2,%3"
[(set_attr "length" "4")
(set_attr "type" "vecsimple")])
