https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77405
H.J. Lu <hjl.tools at gmail dot com> changed:
What |Removed |Added
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Status|NEW |WAITING
CC|hjl at gcc dot gnu.org |hjl.tools at gmail dot
com
--- Comment #14 from H.J. Lu <hjl.tools at gmail dot com> ---
(In reply to Eric Botcazou from comment #11)
> > * config/i386/i386.h (MOVE_MAX_PIECES): Use TImode in 64-bit
> > mode if unaligned SSE load and store are optimal.
>
> Then the SIGBUS is trigged by an SSE intruction operating on unaligned
> memory and I presume that the kernel doesn't patch things up, unlike on
> Linux?
Linux x86 kernel doesn't patch unaligned load/store. GCC should generate
unaligned load/store instructions when memory is misaligned. Why does
GCC think memory is aligned when it is not. Is this misaligned memory
on stack? Please show the instruction where SIGBUS happened.
