https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71976
--- Comment #4 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to Georg-Johann Lay from comment #2)
> Bugzille does not allow me to attach the .combine dump (for reference).
>
> ...anyway the relevant part of the dump is:
>
> In .242r.ud_dce there is the following right shift insn:
>
> (insn 51 50 52 2 (set (reg:QI 16 r16)
> (const_int 40 [0x28])) bug-combin.c:29 71 {movqi_insn}
> (nil))
> (insn 52 51 61 2 (set (reg:DI 18 r18)
> (ashiftrt:DI (reg:DI 18 r18)
> (reg:QI 16 r16))) bug-combin.c:29 1416 {ashrdi3_insn}
> (expr_list:REG_DEAD (reg:QI 16 r16)
> (nil)))
>
> Insn combine tries to macht the combination of these two insns:
>
> Trying 51 -> 52:
> Failed to match this instruction:
> (set (reg:DI 18 r18)
> (reg:DI 18 r18))
> allowing combination of insns 51 and 52
> original costs 4 + 32 = 36
> replacement cost 4
> deferring deletion of insn with uid = 51.
> modifying insn i3 52: r18:DI=r18:DI
> deferring rescan insn with uid = 52.
>
> So the combination is wrong; for some reason the shift is transformed to a
> no-op move and then removed...
Actually the combination is ok (correct in a weird way) and here is why:
this is r15 = 40; r18 = r18 << r16; So r18 << 40 which is undefined as 40 > 16
so GCC decides why not just provide r18 here.
