[Bug tree-optimization/71916] [6/7 Regression] ICE at -O3 on valid code on x86_64-linux-gnu in "maybe_record_trace_start"

[helloqirun at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71916

--- Comment #4 from Qirun Zhang <helloqirun at gmail dot com> ---
(In reply to rguent...@suse.de from comment #3)
> On Tue, 19 Jul 2016, marxin at gcc dot gnu.org wrote:
> 
> > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71916
> > 
> > Martin Liška <marxin at gcc dot gnu.org> changed:
> > 
> >            What    |Removed                     |Added
> > ----------------------------------------------------------------------------
> >                  CC|                            |rguenth at gcc dot gnu.org
> > 
> > --- Comment #2 from Martin Liška <marxin at gcc dot gnu.org> ---
> > Started with r233209:
> > 
> >    2016-02-08   Richard Biener  <rguent...@suse.de>
> > 
> >         PR rtl-optimization/69274
> >         * ira.c (ira_setup_alts): Do not change recog_data.operand
> >         order.
> > 
> >         * gcc.target/i386/addr-sel-1.c: XFAIL.
> 
> This patch is known to change register allocation thus it very likely
> just uncovers a latent issue.

Hi Richard,

I have another testcase. This time, it crashes only in 32-bit mode while the
64-bit mode works just fine.

The ICE trace is exact the same as the original one. I am not sure if they are
the same..


The testcase is:

int a, b, d, f;
volatile int c;
volatile int e;
long long(fn1)() {}
char fn2(int *p1) {
  if (fn1(f))
    e;
}
int *fn3() {}
short fn4() { b = 0; }
void fn5() {
  b = 2;
  a || fn2(fn3(fn4()));
  char g[4];
  int i;
  for (; c; d++)
    ;
  for (e; b < 4; i++)
    g[i] = 9;
  for (; b;)
    ;
}