https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70915
Bug ID: 70915
Summary: Improve loading 0/-1 in VSX registers on PowerPC
Product: gcc
Version: 7.0
Status: UNCONFIRMED
Severity: minor
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: meissner at gcc dot gnu.org
Target Milestone: ---
Right now, the GCC compiler uses XXLXOR to zero a VSX register, and XXLORC (on
power8 and above) to set a register to all 1's. It might be better to prefer to
use the Altivec registers and use a VSPLITSW instruction to load a 0 or -1.
If the register being set to 0/-1 is currently part of a long instruction that
has not completed, the XXLXOR or XXLORC would need to wait for the completion
of the register, even though it does not 'need' the value of the register.
For example, if you do a divide and store the result, and then immediately try
to clear the register to use it for something else, the store would be delayed
until the divide completes, and in this case the logical operation would also
be delayed.
