https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70465
--- Comment #9 from Vladimir Makarov <vmakarov at gcc dot gnu.org> --- (In reply to Jeffrey A. Law from comment #8) > I understand the issues around heuristics. > > Presumably this is the code which identifies cases where we have a single > use register with an associated REG_EQUIV note and we move the insn that > sets the equivalence to the point just before the use? Which has the side > effect of giving is a "bad" ordering in this case (and just as likely may > give us a "good" ordering in other cases). Right. A general solution could be making RA register stack aware or, as Uros wrote, implementing register stack loads reordering in regstack. The both need some efforts as regstack should work with memory dependencies and global RA should work somehow with insn order. Right now IRA has no such infrastructure. It sees a global picture mostly. On other hand LRA works with insns order and work with constraints (like the register stack top), so it could rename registers after all to minimize fxch. Unfortunately its should reorder insns too and it means LRA should work with dependencies. One more place could be the 2nd insn scheduler as it works with dependencies but it lacks register renaming infrastructure. Right now I think that the best place for a general solution would be the regstack. RA and the scheduler are complicated enough to make them eveb more complicated for a rare target. The only questions are does it worth to do and who is going to do this.
