https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70359
--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> --- (In reply to Richard Biener from comment #1) > My #1 bet would be FSM threading. I doubt it as if I read the asm differences correctly, GCC 6 just no longer does store with post increment and that causes register allocation differences. AKA there is no extra jump threading; just extra moves. Like: 68: e1a05004 mov r5, r4 6c: eaffffec b 24 <inttostr+0x24> so it might be caused by out of SSA differences too :)
