https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70220
--- Comment #2 from Wink Saville <wink at saville dot com> ---
(In reply to H.J. Lu from comment #1)
> (In reply to Wink Saville from comment #0)
> > I have identified one possible problem and with this scheme, what if the
> > compiler needs to setup a stack frame by pushing rbp and then moving rsp to
> > rbp, how would that case be handled.
>
> Why should be it a problem unless you don't want to restore RSP and RBP
> to its original values upon returning from ISR. Please provide an example
> here.
Here a possible example, I added a printf and local variables to
timer_reschedule_isr:
void timer_reschedule_isr(struct intr_frame* frame) {
__asm__ volatile(""::: "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp",
"r8", "r9", "r10", "r11", "r12", "r13", "r14",
"r15");
volatile ac_u64 array[3]; // << new
array[2] = get_sp(); // << new
ac_printf("timer_reschedule_isr array[0]=%p\n", array[2]); // << new
tcb_x86 *ptcb = thread_scheduler((ac_u8*)get_sp(), get_ss());
__asm__ volatile("movq %0, %%rsp;" :: "rm" (ptcb->sp) : "rsp");
__asm__ volatile("movw %0, %%ss;" :: "rm" (ptcb->ss));
set_apic_timer_initial_count(ptcb->slice);
__atomic_add_fetch(&timer_reschedule_isr_counter, 1, __ATOMIC_RELEASE);
send_apic_eoi();
} // line 254 <<<<<
The compiler generates an error on the function's closing brace at line 254:
/home/wink/prgs/sadie/arch/x86/libs/thread_x86/srcs/thread_x86.c: In function
'timer_reschedule_isr':
/home/wink/prgs/sadie/arch/x86/libs/thread_x86/srcs/thread_x86.c:254:1: error:
bp cannot be used in asm here
}
If I now remove "rbp" from the clobber list it compiles:
void timer_reschedule_isr(struct intr_frame* frame) {
__asm__ volatile(""::: "rax", "rbx", "rcx", "rdx", "rsi", "rdi", // "rbp", <<
remove
"r8", "r9", "r10", "r11", "r12", "r13", "r14",
"r15");
volatile ac_u64 array[3]; // << new
array[2] = get_sp(); // << new
ac_printf("timer_reschedule_isr array[0]=%p\n", array[2]); // << new
tcb_x86 *ptcb = thread_scheduler((ac_u8*)get_sp(), get_ss());
__asm__ volatile("movq %0, %%rsp;" :: "rm" (ptcb->sp) : "rsp");
__asm__ volatile("movw %0, %%ss;" :: "rm" (ptcb->ss));
set_apic_timer_initial_count(ptcb->slice);
__atomic_add_fetch(&timer_reschedule_isr_counter, 1, __ATOMIC_RELEASE);
send_apic_eoi();
} // line 254 <<<<<
And the generated subroutine prologue/epilogue is:
0000000000100410 <timer_reschedule_isr>:
100410: 55 push %rbp
100411: 48 89 e5 mov %rsp,%rbp
100414: 41 57 push %r15
100416: 41 56 push %r14
100418: 41 55 push %r13
10041a: 41 54 push %r12
10041c: 41 53 push %r11
10041e: 41 52 push %r10
100420: 41 51 push %r9
100422: 41 50 push %r8
100424: 57 push %rdi
100425: 56 push %rsi
100426: 53 push %rbx
100427: 51 push %rcx
100428: 52 push %rdx
100429: 50 push %rax
10042a: 48 83 e4 f0 and $0xfffffffffffffff0,%rsp
10042e: 48 83 ec 20 sub $0x20,%rsp
100432: fc cld
....
10048b: 48 8d 65 90 lea -0x70(%rbp),%rsp
10048f: 58 pop %rax
100490: 5a pop %rdx
100491: 59 pop %rcx
100492: 5b pop %rbx
100493: 5e pop %rsi
100494: 5f pop %rdi
100495: 41 58 pop %r8
100497: 41 59 pop %r9
100499: 41 5a pop %r10
10049b: 41 5b pop %r11
10049d: 41 5c pop %r12
10049f: 41 5d pop %r13
1004a1: 41 5e pop %r14
1004a3: 41 5f pop %r15
1004a5: 5d pop %rbp
1004a6: 48 cf iretq
So now the compiler saves/restores rbp and align's and adjusts rsp in the
prologue/epilogue code, is this something the programmer could do properly,
maybe but I was speculating it might be a problem.
