https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69459
Jakub Jelinek <jakub at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |uros at gcc dot gnu.org,
| |vmakarov at gcc dot gnu.org
--- Comment #4 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
So, we have here:
(insn 42 41 43 2 (set (reg:V4SI 318)
(const_vector:V4SI [
(const_int -1 [0xffffffffffffffff])
(const_int -1 [0xffffffffffffffff])
(const_int -1 [0xffffffffffffffff])
(const_int -1 [0xffffffffffffffff])
])) pr69459.c:14 1220 {*movv4si_internal}
(expr_list:REG_EQUIV (const_vector:V4SI [
(const_int -1 [0xffffffffffffffff])
(const_int -1 [0xffffffffffffffff])
(const_int -1 [0xffffffffffffffff])
(const_int -1 [0xffffffffffffffff])
])
(nil)))
...
(insn 245 242 246 4 (set (reg/v:V4SI 295 [ v16u32_1 ])
(vec_merge:V4SI (vec_duplicate:V4SI (const_int 4160055 [0x3f7a37]))
(reg:V4SI 318)
(const_int 1 [0x1]))) pr69459.c:23 2489 {vec_setv4si_0}
(expr_list:REG_DEAD (reg:V4SI 318)
(expr_list:REG_EQUAL (const_vector:V4SI [
(const_int 4160055 [0x3f7a37])
(const_int -1 [0xffffffffffffffff])
(const_int -1 [0xffffffffffffffff])
(const_int -1 [0xffffffffffffffff])
])
(nil))))
and LRA changes this into:
...
(insn 245 481 246 4 (set (reg/v:V4SI 24 xmm3 [orig:295 v16u32_1 ] [295])
(vec_merge:V4SI (vec_duplicate:V4SI (mem/c:SI (plus:DI (reg/f:DI 7 sp)
(const_int -120 [0xffffffffffffff88])) [5 %sfp+-256 S4
A128]))
(const_vector:V4SI [
(const_int -1 [0xffffffffffffffff])
(const_int -1 [0xffffffffffffffff])
(const_int -1 [0xffffffffffffffff])
(const_int -1 [0xffffffffffffffff])
])
(const_int 1 [0x1]))) pr69459.c:23 2489 {vec_setv4si_0}
(expr_list:REG_EQUAL (const_vector:V4SI [
(const_int 4160055 [0x3f7a37])
(const_int -1 [0xffffffffffffffff])
(const_int -1 [0xffffffffffffffff])
(const_int -1 [0xffffffffffffffff])
])
(nil)))
This is because the "C" constraint allows not just CONST0_RTX, but also
selected all ones vectors, including the V4SI all ones vector.
The vec_setv4si_0 insn uses the "C" constraints with "vector_move_operand"
predicate, the all ones vector fails the vector_move_operand predicate, but for
whatever reason LRA doesn't try to undo it and doesn't invalidate the cached
insn code, so we happily assembly it. But instead of the desired { 0x3f7a37,
-1, -1, -1 } vector we get { 0x3f7a37, 0, 0, 0 }.
I'd say the i386 backend just should add a new constraint for CONST0_RTX only
and use it wherever the all ones is not allowed. As "C" is documented,
probably the new "BC" constraint should be const0/CONST0_RTX only, and I think
at least the vector_move_operand, reg_or_0_operand and likely the
const_int_operand cases too should be changed to "BC". At least that way the
RA and other spots will not try to satisfy it with something that can't match.
And then there is the question if and what should change on the LRA side.
i386.md: (match_operand:XI 1 "vector_move_operand" "C ,vm,v"))]
i386.md: (match_operand:OI 1 "vector_move_operand" "C ,vm,v"))]
i386.md: (match_operand:TI 1 "general_operand" "riFo,re,C,vm,v"))]
i386.md: (match_operand:DI 1 "general_operand" "riFo,riF,Z,rem,i,re,C
,*y,m ,*y,*Yn,r ,C ,*v,m ,*v,v,*Yj,*v,r ,*Yj ,*Yn ,*r ,*km,*k,*k"))]
i386.md: (match_operand:SI 1 "general_operand" "g ,re,C ,*y,*y ,rm ,C
,*v,m ,*v,*Yj,*v,r ,*krm,*k"))]
i386.md: (match_operand:TF 1 "general_operand" "C
,xm,x,*roF,*rC"))]
i386.md: (match_operand:XF 1 "general_operand" "fm,f,G,roF,r , *roF,*r,F
,C,roF,rF"))]
i386.md: (match_operand:DF 1 "general_operand" "Yf*fm,Yf*f,G ,roF,r
,*roF,*r,F ,rm,rC,C ,F ,C,v,m,v,C ,*x,m ,*x,Yj,r ,roF,rF,rmF,rC"))]
i386.md: (match_operand:SF 1 "general_operand" "Yf*fm,Yf*f,G
,rmF,rF,C,v,m,v,Yj,r ,*y ,m ,*y,*Yn,r ,rmF,rF"))]
i386.md: [(match_operand:<CSGNVMODE> 1 "vector_move_operand" "xmC")
mmx.md: (match_operand:MMXMODE 1 "vector_move_operand" "rCo,rC,C,rm,rC,C ,!y,m
,?!y,?!Yn,r ,C,v,m,v,C ,*x,m ,*x,Yj,r ,*Yj,!Yn"))]
mmx.md: (match_operand:SF 2 "vector_move_operand" "ym,C")))]
mmx.md: (match_operand:SI 2 "vector_move_operand" "ym,C")))]
sse.md: (match_operand:VMOVE 1 "nonimmediate_or_sse_const_operand" "C
,vm,v"))]
sse.md: (match_operand:V48_AVX512VL 2 "vector_move_operand" "0C,0C")
sse.md: (match_operand:VI12_AVX512VL 2 "vector_move_operand" "0C,0C")
sse.md: (match_operand:V4SF 2 "vector_move_operand" "0C")
sse.md: (match_operand:V4SF 3 "vector_move_operand" "0C")
sse.md: (match_operand:V4SF 7 "vector_move_operand" "0C")
sse.md: (match_operand:SF 2 "reg_or_0_operand" " x,C,*y, C")))]
sse.md: (match_operand:VI4F_128 1 "vector_move_operand" " C , C,C,C ,C,0,v,0
,0 ,x ,0 ,0 ,0")
sse.md: (match_operand:<ssehalfvecmode> 2 "vector_move_operand" "0C")
sse.md: (match_operand:V2DF 3 "vector_move_operand" "0C")
sse.md: (match_operand:V2DF 3 "vector_move_operand" "0C")
sse.md: (match_operand:V2DF 5 "vector_move_operand" "0C")
sse.md: (match_operand:V2DF 1 "vector_move_operand" " C,0,x,0,x,x,o,o,0,0
,0")
sse.md: (match_operand:DF 2 "vector_move_operand" " x,x,v,1,1,m,m,C,x,m")))]
sse.md: (match_operand:PMOV_DST_MODE_1 2 "vector_move_operand" "0C,0")
sse.md: (match_operand:V32QI 2 "vector_move_operand" "0C,0")
sse.md: (match_operand:PMOV_DST_MODE_2 2 "vector_move_operand" "0C,0")
sse.md: (match_operand:V16QI 2 "vector_move_operand" "0C")
sse.md: (match_operand:V16QI 2 "vector_move_operand" "0C")
sse.md: (match_operand:V16QI 2 "vector_move_operand" "0C")
sse.md: (match_operand:V8HI 2 "vector_move_operand" "0C")
sse.md: (match_operand:V8HI 2 "vector_move_operand" "0C")
sse.md: (match_operand:V4SI 2 "vector_move_operand" "0C")
sse.md: (match_operand:V16QI 2 "vector_move_operand" "0C")
sse.md: (match_operand:VI48_AVX512VL 3 "vector_move_operand" "0C")
sse.md: (match_operand:VI12_AVX512VL 3 "vector_move_operand" "0C")
sse.md: (match_operand:VI48_AVX512VL 3 "vector_move_operand" "0C")
sse.md: (match_operand:VI12_AVX512VL 3 "vector_move_operand" "0C")
sse.md: (match_operand:V4SI 1 "reg_or_0_operand" "C ,C ,C,0,x")
sse.md: (match_operand:SI 2 "vector_move_operand" " rm,rm,rm,Yr,*x,x, C,*ym,
C")))]
sse.md: (match_operand:SI 2 "reg_or_0_operand" " x,C ,C, x,C,*y,C")))]
sse.md: (match_operand:DI 2 "vector_move_operand" "*rm,rm,rm,C ,C ,C
,x,x,x,m,m")))]
sse.md: (match_operand:VI1_AVX512 4 "vector_move_operand" "0C")
sse.md: (match_operand:VI48_AVX512VL 2 "vector_move_operand" "0C")
sse.md: (match_operand:VI12_AVX512VL 2 "vector_move_operand" "0C")
sse.md: [(match_operand 3 "const_int_operand" "C,n,n")])))]
sse.md: [(match_operand 3 "const_int_operand" "C,n,n")])))]
sse.md: (match_operand:<ssehalfvecmode> 2 "vector_move_operand" "xm,C")))]
sse.md: (match_operand:VI48F 2 "vector_move_operand" "0C")
sse.md: (match_operand:VI48F 2 "vector_move_operand" "0C,0C")
subst.md: (match_operand:SUBST_V 2 "vector_move_operand" "0C")
subst.md: (match_operand:SUBST_V 2 "const0_operand" "C")
