https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69052
Ilya Enkovich <ienkovich at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |ienkovich at gcc dot gnu.org
--- Comment #6 from Ilya Enkovich <ienkovich at gcc dot gnu.org> ---
(In reply to amker from comment #5)
> Not sure if stage4 is a good time for a new hook either.
>
> Any ideas?
We can try to improve i386 address recognition to ignore operands order. With
this patch:
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 34b57a4..b13d3f6 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -14111,8 +14111,16 @@ ix86_decompose_address (rtx addr, struct ix86_address
*out)
{
if (n >= 4)
return 0;
- addends[n++] = XEXP (op, 1);
- op = XEXP (op, 0);
+ if (GET_CODE (XEXP (op, 1)) == PLUS)
+ {
+ addends[n++] = XEXP (op, 0);
+ op = XEXP (op, 1);
+ }
+ else
+ {
+ addends[n++] = XEXP (op, 1);
+ op = XEXP (op, 0);
+ }
}
while (GET_CODE (op) == PLUS);
if (n >= 4)
I get following ASM:
.L5:
movl ind@GOTOFF(%ebx,%esi,4), %eax
movl 12(%esp), %edi
movl %ebp, (%edi,%eax,4)
