https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69447
Richard Henderson <rth at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Keywords| |ra
CC| |rth at gcc dot gnu.org
--- Comment #3 from Richard Henderson <rth at gcc dot gnu.org> ---
This is a register allocation problem.
From the ira dump:
(insn 17 16 18 2 (set (reg/v:DI 111 [ u64_3 ])
(mult:DI (zero_extend:DI (reg:SI 183 [ u64_3 ]))
(zero_extend:DI (reg:SI 183 [ u64_3 ])))) z.c:10 54 {*umulsidi3_v6}
(expr_list:REG_DEAD (reg:SI 183 [ u64_3 ])
(nil)))
(insn 19 18 21 2 (set (subreg:SI (reg/v:DI 111 [ u64_3 ]) 4)
(plus:SI (ashift:SI (reg:SI 142)
(const_int 1 [0x1]))
(subreg:SI (reg/v:DI 111 [ u64_3 ]) 4))) z.c:10 232 {*add_shiftsi}
(expr_list:REG_DEAD (reg:SI 142)
(nil)))
...
(insn 23 22 24 2 (set (reg/v:SI 117 [ u8_0 ])
(ior:SI (reg:SI 0 r0 [ u8_0 ])
(const_int 3 [0x3]))) z.c:14 97 {*iorsi3_insn}
(expr_list:REG_DEAD (reg:SI 0 r0 [ u8_0 ])
(nil)))
but then during reload, Reg111 is allocated to r4:r5 in insn 17.
But Reg117 is also allocated to r5 in insn 23, clobbering the
high-part store of Reg111 from insn 19.
