https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69112
Bug ID: 69112
Summary: MIssing register assignment
Product: gcc
Version: 6.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: ysato at users dot sourceforge.jp
Target Milestone: ---
Created attachment 37204
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=37204&action=edit
reproduce sample
I compiled this inline assembler functions.
__asm__ volatile("mvfc psw, %2\n\t"
"clrpsw i\n\t"
"btst %3, %1.b\n\t"
"bset %3, %1.b\n\t"
"scnz.l %0\n\t"
"mvtc %2, psw"
: "=r"(result),"+m"(*b_addr),"=r"(psw)
:"ri"(nr & 7):"cc");
I got this result. The result which isn't expected.
%2 and %3 is same...
rx-elf-gcc -Os
mvfc psw, r1
clrpsw i
btst r1, [r2].b
bset r1, [r2].b
scnz.l r15
mvtc r1, psw
"-O2" is good.
mvfc psw, r2
clrpsw i
btst r4, [r14].b
bset r4, [r14].b
scnz.l r4
mvtc r2, psw
Attached reproduce source.
