https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68543
--- Comment #2 from Michael Collison <michael.collison at linaro dot org> --- Great idea I will look into this. On 12/10/2015 4:02 AM, ktkachov at gcc dot gnu.org wrote: > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68543 > > --- Comment #1 from ktkachov at gcc dot gnu.org --- > Maybe we can avoid defining custom expanders if we define > WORD_REGISTER_OPERATIONS for aarch64. > It's defined for arm and the documentation hints that it should be true for > most RISC targets. > > Then the default fallback codegen for the given example is much improved: > foo: > uxth x0, w0 > uxth x1, w1 > mul x0, x0, x1 > cmp x0, x0, sxtw > bne .L10 > ret > .L10: > stp x29, x30, [sp, -16]! > add x29, sp, 0 > bl abort > > > However, we need to investigate the other codegen effects that come with > WORD_REGISTER_OPERATIONS, in particular to make sure that the aarch64 patterns > cope with the slightly different strategies of using subregs and sign/zero > extends in combine >
