https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67383
renlin at gcc dot gnu.org changed:
What |Removed |Added
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CC| |renlin at gcc dot gnu.org
--- Comment #5 from renlin at gcc dot gnu.org ---
(In reply to Vladimir Makarov from comment #4)
> I've tried to reproduce it on gcc-4.9 branch as of today but failed. The
> problem with constraints and overlapped hard regs was probably fixed by
> backported patches.
>
> Still I have another problem:
>
> ../lib/mm/mm.c: In function ‘chunk_node’:
> ../lib/mm/mm.c:430:1: internal compiler error: in assign_by_spills, at
> lra-assigns.c:1357
> 0x853dd5 assign_by_spills
>
> /home/cygnus/vmakarov/build1/gcc-4.9-branch/gcc/gcc/lra-assigns.c:1357
> 0x854617 lra_assign()
>
> /home/cygnus/vmakarov/build1/gcc-4.9-branch/gcc/gcc/lra-assigns.c:1503
> 0x84de9c lra(_IO_FILE*)
> /home/cygnus/vmakarov/build1/gcc-4.9-branch/gcc/gcc/lra.c:2388
> 0x80ca16 do_reload
> /home/cygnus/vmakarov/build1/gcc-4.9-branch/gcc/gcc/ira.c:5474
> 0x80ca16 rest_of_handle_reload
> /home/cygnus/vmakarov/build1/gcc-4.9-branch/gcc/gcc/ira.c:5615
> 0x80ca16 execute
> /home/cygnus/vmakarov/build1/gcc-4.9-branch/gcc/gcc/ira.c:5644
> Please submit a full bug report,
> with preprocessed source if appropriate.
> Please include the complete backtrace with any bug report.
> See <http://gcc.gnu.org/bugs.html> for instructions.
>
> The problem is in assigning a hard reg to reload pseudo 442 for insns
>
> Choosing alt 0 in insn 153: (0) =&r (1) %0 (2) r {*arm_adddi3}
> Creating newreg=441, assigning class GENERAL_REGS to r441
> Creating newreg=442 from oldreg=268, assigning class GENERAL_REGS to
> r442
> 153: {r441:DI=r441:DI+r442:DI;clobber cc:CC;}
> REG_DEAD r268:DI
> REG_UNUSED cc:CC
> REG_EQUIV [sp:SI+0x10]
> Inserting insn reload before:
> 642: r441:DI=[sp:SI+0x8]
> 644: r442:DI=r268:DI
> Inserting insn reload after:
> 643: [sp:SI+0x10]=r441:DI
>
> We canot use hard reg 0, 1, 2 as they live through insn 153:
>
> ...
> 153: {r272:DI=r268:DI+r159:DI;clobber cc:CC;}
> REG_DEAD r268:DI
> REG_UNUSED cc:CC
> REG_EQUIV [sp:SI+0x10]
> ...
> 159: call [`debug_printf'] argc:0x20
> REG_DEAD r1:SI
> REG_DEAD r0:SI
> REG_DEAD r2:DI
>
> Hard reg 7 (FP), 9 (thread), 10 (pic), 13 (sp), 15 (pc) are fixed. So
> we have only one hole for DI value containing 2 regs (4, 5) and pair
> (4,5) is assigned to 441 and there are no regs for 442.
In this particular case, hard register 12 is free, and hard register 11 can be
spilled to accommodate this DImode pseudo register.
However, the target hook HARD_REGNO_MODE_OK rejects register pairs start from
odd number (11 in this case.) So find_hard_regno_for() failed.
I have found r209615 relaxes the target hook. In thumb2 mode, any register pair
is allowed. I have verified, it fix this ICE.
I will do a full regression test first, If no new issues, I will backport it to
branch 4.9
