[Bug target/67037] [4.9/5/6 Regression] Wrong code at -O1 and above on ARM

[bernd.edlinger at hotmail dot de]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67037

--- Comment #4 from Bernd Edlinger <bernd.edlinger at hotmail dot de> ---
I believe that when we see this in testcase.c.232r.reload

   73: [r166:SI++]=r142:SI#0
      REG_DEAD r142:SI
      REG_INC r149:SI
    Inserting insn reload before:
  153: r166:SI=[afp:SI+0x14f8]
    Inserting insn reload after:
  154: [afp:SI+0x14f8]=r166:SI

the insns before and after have the same address rtx
and while the insn 154 is transformed to:

  155: r3:SI=sp:SI+0x14f8
  154: [r3:SI]=r1:SI

insn 153's address suddenly becomes [r3:SI] too.

The following patch seems to fix it:

--- lra-constraints.c.jj        2015-09-25 23:06:08.000000000 +0200
+++ lra-constraints.c   2015-09-29 13:29:01.695783261 +0200
@@ -1339,7 +1339,7 @@ process_addr_reg (rtx *loc, bool check_o
   if (after != NULL)
     {
       start_sequence ();
-      lra_emit_move (reg, new_reg);
+      lra_emit_move (before_p ? copy_rtx (reg) : reg, new_reg);
       emit_insn (*after);
       *after = get_insns ();
       end_sequence ();