https://gcc.gnu.org/bugzilla/show_bug.cgi?id=50749
Urja Rannikko <urjaman at gmail dot com> changed:
What |Removed |Added
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CC| |urjaman at gmail dot com
--- Comment #20 from Urja Rannikko <urjaman at gmail dot com> ---
I'll add a note here that this seems to also affect the AVR target when it is
under register pressure and cant use Z or Y registers which can do Z+n /Y+n
addressing, it ends up doing really stupid things with X register (aka r26:r27)
(which could post-inc):
adiw r26, 0x01
ld r24, X
sbiw r26, 0x01
(followed by adiw r26, 2...)
This was my test case for showing this behaviour on AVR:
unsigned char test_0 (unsigned char* p1, unsigned char *p2, unsigned char *p3)
{
unsigned char r = 0;
r += *p1++;
r += *p2++;
r += *p3++;
r += *p1++;
r += *p2++;
r += *p3++;
r += *p1++;
r += *p2++;
r += *p3++;
return r;
}
This note added for anyone later trying to google for this after seeing that X
reg stupidity on AVR, sorry for maybe-a-bit-noise ...
