[Bug target/66049] Few AArch64 extend and add with shift tests generates sub optimal code with trunk gcc 6.0.

[vekumar at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66049

--- Comment #1 from vekumar at gcc dot gnu.org ---
We need patterns based on shifts to match with combiner generated.

Below patch fixes them.

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 1c2c5fb..c5a640d 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1555,6 +1555,23 @@
   [(set_attr "type" "alus_shift_imm")]
 )

+(define_insn "*adds_shift_imm_<mode>"
+  [(set (reg:CC_NZ CC_REGNUM)
+        (compare:CC_NZ
+         (plus:GPI (ASHIFT:GPI
+                    (match_operand:GPI 1 "register_operand" "r")
+                    (match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))
+                   (match_operand:GPI 3 "register_operand" "r"))
+         (const_int 0)))
+   (set (match_operand:GPI 0 "register_operand" "=r")
+        (plus:GPI (ASHIFT:GPI (match_dup 1) (match_dup 2))
+                  (match_dup 3)))]
+  ""
+  "adds\\t%<w>0, %<w>3, %<w>1, <shift> %2"
+  [(set_attr "type" "alus_shift_imm")]
+)
+
+
 (define_insn "*subs_mul_imm_<mode>"
   [(set (reg:CC_NZ CC_REGNUM)
        (compare:CC_NZ
@@ -1571,6 +1588,23 @@
   [(set_attr "type" "alus_shift_imm")]
 )

+(define_insn "*subs_shift_imm_<mode>"
+  [(set (reg:CC_NZ CC_REGNUM)
+        (compare:CC_NZ
+         (minus:GPI (match_operand:GPI 1 "register_operand" "r")
+                    (ASHIFT:GPI
+                     (match_operand:GPI 2 "register_operand" "r")
+                     (match_operand:QI 3 "aarch64_shift_imm_<mode>" "n")))
+         (const_int 0)))
+   (set (match_operand:GPI 0 "register_operand" "=r")
+        (minus:GPI (match_dup 1)
+                   (ASHIFT:GPI (match_dup 2) (match_dup 3))))]
+  ""
+  "subs\\t%<w>0, %<w>1, %<w>2, <shift> %3"
+  [(set_attr "type" "alus_shift_imm")]
+)
+
+
 (define_insn "*adds_<optab><ALLX:mode>_<GPI:mode>"
   [(set (reg:CC_NZ CC_REGNUM)
        (compare:CC_NZ
@@ -1599,6 +1633,41 @@
   [(set_attr "type" "alus_ext")]
 )

+(define_insn "*adds_<optab><ALLX:mode>_shft_<GPI:mode>"
+  [(set (reg:CC_NZ CC_REGNUM)
+        (compare:CC_NZ
+         (plus:GPI (ashift:GPI (ANY_EXTEND:GPI
+                                (match_operand:ALLX 1 "register_operand" "r"))
+                               (match_operand 2 "aarch64_imm3" "Ui3"))
+                   (match_operand:GPI 3 "register_operand" "r"))
+        (const_int 0)))
+   (set (match_operand:GPI 0 "register_operand" "=rk")
+        (plus:GPI (ashift:GPI (ANY_EXTEND:GPI (match_dup 1))
+                              (match_dup 2))
+                  (match_dup 3)))]
+  ""
+  "adds\\t%<GPI:w>0, %<GPI:w>3, %<GPI:w>1, <su>xt<ALLX:size> %2"
+  [(set_attr "type" "alus_ext")]
+)
+
+(define_insn "*subs_<optab><ALLX:mode>_shft_<GPI:mode>"
+  [(set (reg:CC_NZ CC_REGNUM)
+        (compare:CC_NZ
+         (minus:GPI (match_operand:GPI 1 "register_operand" "r")
+                    (ashift:GPI (ANY_EXTEND:GPI
+                                (match_operand:ALLX 2 "register_operand" "r"))
+                               (match_operand 3 "aarch64_imm3" "Ui3")))
+        (const_int 0)))
+   (set (match_operand:GPI 0 "register_operand" "=rk")
+        (minus:GPI (match_dup 1)
+                    (ashift:GPI (ANY_EXTEND:GPI (match_dup 2))
+                              (match_dup 3))))]
+  ""
+  "subs\\t%<GPI:w>0, %<GPI:w>1, %<GPI:w>2, <su>xt<ALLX:size> %3"
+  [(set_attr "type" "alus_ext")]
+)
+
+
 (define_insn "*adds_<optab><mode>_multp2"
   [(set (reg:CC_NZ CC_REGNUM)
        (compare:CC_NZ
@@ -1909,6 +1978,22 @@
   [(set_attr "type" "alu_ext")]
 )

+(define_insn "*add_uxt<mode>_shift2"
+  [(set (match_operand:GPI 0 "register_operand" "=rk")
+        (plus:GPI (and:GPI
+                   (ashift:GPI (match_operand:GPI 1 "register_operand" "r")
+                             (match_operand 2 "aarch64_imm3" "Ui3"))
+                   (match_operand 3 "const_int_operand" "n"))
+                  (match_operand:GPI 4 "register_operand" "r")))]
+  "aarch64_uxt_size (INTVAL (operands[2]), INTVAL (operands[3])) != 0"
+  "*
+  operands[3] = GEN_INT (aarch64_uxt_size (INTVAL(operands[2]),
+                                           INTVAL (operands[3])));
+  return \"add\t%<w>0, %<w>4, %<w>1, uxt%e3 %2\";"
+  [(set_attr "type" "alu_ext")]
+)
+
+
 ;; zero_extend version of above
 (define_insn "*add_uxtsi_multp2_uxtw"
   [(set (match_operand:DI 0 "register_operand" "=rk")
@@ -2165,6 +2250,22 @@
   [(set_attr "type" "alu_ext")]
 )

+(define_insn "*sub_uxt<mode>_shift2"
+  [(set (match_operand:GPI 0 "register_operand" "=rk")
+        (minus:GPI (match_operand:GPI 4 "register_operand" "rk")
+                   (and:GPI
+                    (ashift:GPI (match_operand:GPI 1 "register_operand" "r")
+                              (match_operand 2 "aarch64_imm3" "Ui3"))
+                    (match_operand 3 "const_int_operand" "n"))))]
+  "aarch64_uxt_size (INTVAL (operands[2]),INTVAL (operands[3])) != 0"
+  "*
+  operands[3] = GEN_INT (aarch64_uxt_size (INTVAL (operands[2]),
+                                           INTVAL (operands[3])));
+  return \"sub\t%<w>0, %<w>4, %<w>1, uxt%e3 %2\";"
+  [(set_attr "type" "alu_ext")]
+)
+
+
 ;; zero_extend version of above
 (define_insn "*sub_uxtsi_multp2_uxtw"
   [(set (match_operand:DI 0 "register_operand" "=rk")