[Bug target/65952] [AArch64] Will not vectorize storing induction of pointer addresses for LP64

[alalaw01 at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65952

--- Comment #4 from alalaw01 at gcc dot gnu.org ---
Hmmm. Yes. Well, x * 16 = x << 4, of course. Or, in theory something like VRP
could let us see that

  # i_12 = PHI <i_9(4), 0(2)>
  # ivtmp_18 = PHI <ivtmp_17(4), 4(2)>
  _5 = (long unsigned int) i_12;
  _6 = _5 * 16;
  _7 = pretmp_11 + _6;
  ptrs[i_12] = _7;
  i_9 = i_12 + 1;

could be rewritten to something like

  # i_12 = PHI <i_9(4), 0(2)>
  # ivtmp_18 = PHI <ivtmp_17(4), 4(2)>
  _5 = _12 * 16;
  _6 = (long unsigned int) _5;
  _7 = pretmp_11 + _6;
  ptrs[i_12] = _7;
  i_9 = i_12 + 1;

which would then be vectorizable.