https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65456
Alan Modra <amodra at gmail dot com> changed:
What |Removed |Added
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CC| |amodra at gmail dot com
--- Comment #14 from Alan Modra <amodra at gmail dot com> ---
This part
|| (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
|| (MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) \
&& (ALIGN) < 32) \
is wrong for power8 too. See "POWER8 Processor User’s Manual for the
Single-Chip Module", section 2.1.4 Storage Access Alignment Support Overview.
According to that, alignment interrupt does not occur on misaligned floating
point loads and stores, except for the quadword insns. Which seems to
contradict "Power ISA Version 2.07", section 6.5.8 Alignment Interrupt. I
guess the ISA doc needs another update.
