https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65153
--- Comment #5 from Kazumoto Kojima <kkojima at gcc dot gnu.org> --- Created attachment 34828 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=34828&action=edit reduced testcase Looks an interesting "why didn't we see it?" target bug. The problem happens at peephole2 phase. The insn sequence (insn 353 103 105 4 (set (reg:SI 1 r1) (reg:SI 6 r6))) (insn 105 353 106 4 (set (reg:SI 7 r7) (ashift:SI (reg:SI 7 r7) (reg:SI 0 r0)))) (insn 106 105 107 4 (set (reg/v:SI 6 r6) (ior:SI (reg:SI 6 r6) (reg:SI 7 r7)))) is tested by the complex peephole (define_peephole2 [(set (match_operand 0 "any_register_operand" "") (match_operand 1 "any_register_operand" "")) (set (match_operand 2 "any_register_operand" "") (match_operand 3 "" "")) (set (match_operand 4 "" "") (match_operand 5 "" ""))] "(HARD_REGNO_NREGS (REGNO (operands[0]), GET_MODE (operands[2])) <= HARD_REGNO_NREGS (REGNO (operands[0]), GET_MODE (operands[0]))) && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[2]) && ! FIND_REG_INC_NOTE (peep2_next_insn (2), operands[0]) && ! FIND_REG_INC_NOTE (peep2_next_insn (2), operands[2]) && ! reg_overlap_mentioned_p (operands[0], operands[3]) && ! reg_overlap_mentioned_p (operands[2], operands[0]) && ! reg_overlap_mentioned_p (operands[0], operands[1]) && (REGNO_REG_CLASS (REGNO (operands[0])) == REGNO_REG_CLASS (REGNO (operands[2]))) && (REGNO_REG_CLASS (REGNO (operands[1])) == REGNO_REG_CLASS (REGNO (operands[0])))" [(set (match_dup 0) (match_dup 3)) (set (match_dup 4) (match_dup 5))] { ... This peephole2 in sh.md tries to replace operands[0] with operands[1] and operands[2] with operands[0] in operands[4]/operands[5]. In our case, operands[5] is (ior:SI (reg:SI 6 r6) (reg:SI 7 r7)) and the peephole tries to do term rewriting r1 -> r6, r7 -> r1. This peephole fails after all and then tries to restore operands[5] with term rewriting r6 -> r1, r1 -> r7. Unfortunately this can't reverse the first term rewriting and yields (ior:SI (reg:SI 1 r1) (reg:SI 7 r7)). Thus we got a wrong insn (set (reg/v:SI 6 r6) (ior:SI (reg:SI 1 r1) (reg:SI 7 r7))).
