https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212
--- Comment #25 from Kazumoto Kojima <kkojima at gcc dot gnu.org> --- Created attachment 33524 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=33524&action=edit Reduced test case for ICE in assign_by_spill I've looked into what is going on for the ICE in assign_by_spill. The above test case ICEs on sh-elf with "-m4 -ml -O1 -ftree-parallelize-loops=4 -ftree-vectorize". .ira and .reload dumps show that the load and store insns 42: r208:SI=[r202:SI+r185:SI] 43: [r207:SI+r200:SI]=r218:HI // r218 = subreg:HI r208 are reloaded like as 73: r217:SI=r200:SI 79: r223:SI=r185:SI 74: r218:HI=[r202:SI+r223:SI] 43: [r207:SI+r217:SI]=r218:HI and R0_REGS is assigned to both r217 and r223 because the only register R0 can be used as the index register on SH. .reload says that the original insn 42 is deleted and the source operand r218 of insn 43 is substituted with its equiv [r202:SI+r185:SI]. It seems that it works also for SH if reload insn 73 was inserted at just before insn 43. I've attached .reload dump for this too.
