http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59810
Bug ID: 59810
Summary: [AArch64] LDn/STn implementations are not
ABI-conformant for bigendian.
Product: gcc
Version: 4.9.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: belagod at gcc dot gnu.org
Permuted loads/stores implemented in the aarch64 backend do not conform to
AArch64 ABI for bigendian. The ABI states that
"... On a little endian system this means that element 0 will always contain
the lowest addressed element of a short vector; on a big endian system element
0 will contain the highest addressed element of a short vector."
In the implementations of vec_loadlanes and vec_storelanes in aarch64-simd.md,
they are just loaded lane-wise for both endianness. This may be correct for
little endian, but for bigendian, this is the reversed order. Because the
architecture does not offer a way to perform opaque loads/stores(LDR q, STR q)
for permuted loads, the lanes will need to be reversed after permuted loading
and reversed before permuted storing.
