http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58416
Richard Biener <rguenth at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Target| |i?86-*-*
--- Comment #2 from Richard Biener <rguenth at gcc dot gnu.org> ---
It is SRA that transforms
MCOp.DoubleVal = 0.0;
MCOp.IntVal = Val_3(D);
*dest_5(D) = MCOp;
into
MCOp$DoubleVal_7 = 0.0;
_8 = VIEW_CONVERT_EXPR<double>(Val_3(D));
MCOp$DoubleVal_4 = _8;
MEM[(union MyClass *)dest_5(D)] = MCOp$DoubleVal_4;
simplifying into
_6 = VIEW_CONVERT_EXPR<double>(Val_3(D));
MEM[(union MyClass *)dest_4(D)] = _6;
and
(insn 7 6 0 (set (mem:DF (reg/v/f:SI 60 [ dest ]) [0 MEM[(union MyClass
*)dest_4(D)]+0 S8 A32])
(subreg:DF (reg/v:DI 61 [ Val ]) 0)) t.C:15 -1
(nil))
causes a reload:
(insn 7 11 12 2 (set (reg:DF 8 st [62])
(mem/c:DF (plus:SI (reg/f:SI 7 sp)
(const_int 8 [0x8])) [0 Val+0 S8 A32])) t.C:15 134
{*movdf_internal}
(nil))
(insn 12 7 0 2 (set (mem:DF (reg/v/f:SI 0 ax [orig:60 dest ] [60]) [0
MEM[(union MyClass *)dest_4(D)]+0 S8 A32])
(reg:DF 8 st [62])) t.C:15 134 {*movdf_internal}
(expr_list:REG_DEAD (reg:DF 8 st [62])
(expr_list:REG_DEAD (reg/v/f:SI 0 ax [orig:60 dest ] [60])
(nil))))
where *movdf_internal simply doesn't properly preserve sNaN.
It looks wrong for DFmode move instructions to not preserve a IEEE defined
flag. I suppose it would be also wrong to not preserve the exact bit pattern
(think of canonicalizing NaNs).