http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58166
Richard Earnshaw <rearnsha at gcc dot gnu.org> changed:
What |Removed |Added
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CC| |rearnsha at gcc dot gnu.org,
| |vmakarov at redhat dot com
--- Comment #4 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
Vlad,
Would you mind commenting on this please?
I suspect it's related to the fact that REG_ALLOC_ORDER on ARM is
{r3, r2, r1, r0, IP, LR, r4, ...}
Which is done to encourage register allocation to use the argument registers
that are least likely to be used for parameters.
What seems to happen is that the compiler picks r3 and r4 over r2 and r3, even
though r4 is a callee saved register and r2 is unused.
Is IRA handling the cost of additional registers for multi-reg pseduos
correctly?
