http://gcc.gnu.org/bugzilla/show_bug.cgi?id=13423
--- Comment #4 from Oleg Endo <olegendo at gcc dot gnu.org> 2013-03-11 19:56:20 UTC --- (In reply to comment #3) > > ideally, this would be something like (no insn scheduling applied): > > fmov.s @r4+,fr0 > fmov.s @r4+,fr1 > fmov.s @r4+,fr2 > fmov.s @r4+,fr3 > > fmov.s @r5+,fr4 > fmov.s @r5+,fr5 > fmov.s @r5+,fr6 > fmov.s @r5+,fr7 > > fadd fr4,fr0 > fadd fr5,fr1 > fadd fr6,fr2 > fadd fr7,fr3 > > fmov.s fr3,@-r4 > fmov.s fr2,@-r4 > fmov.s fr1,@-r4 > fmov.s fr0,@-r4 Which would probably require a working address mode selection optimization pass, see PR 56590. As for the ABI issue when passing vectors by value, I've created PR 56592 that describes a proposed new vector ABI for SH.
