http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56441
--- Comment #10 from gnugcc at emblocks dot org 2013-02-26 17:24:52 UTC ---
The ARM branch, sorry I see now that the trunk is different.
Arm branch:
;; The r/r/k alternative is required when reloading the address
;; (plus (reg rN) (reg sp)) into (reg rN). In this case reload will
;; put the duplicated register first, and not try the commutative version.
(define_insn_and_split "*arm_addsi3"
[(set (match_operand:SI 0 "s_register_operand" "=l, r, k,r,r, k, l,
r, k,r, k, r")
(plus:SI (match_operand:SI 1 "s_register_operand" "%0, rk,k,r,rk,k, 0,
rk,k,rk,k, rk")
(match_operand:SI 2 "reg_or_int_operand" "Py,rI,rI,k,Pj,Pj,Pv,L,
L,PJ,PJ,?n")))]
"TARGET_32BIT"
"@
add%?\\t%0, %1, %2
add%?\\t%0, %1, %2
add%?\\t%0, %1, %2
add%?\\t%0, %2, %1
addw%?\\t%0, %1, %2
addw%?\\t%0, %1, %2
sub%?\\t%0, %1, #%n2
sub%?\\t%0, %1, #%n2
sub%?\\t%0, %1, #%n2
subw%?\\t%0, %1, #%n2
subw%?\\t%0, %1, #%n2
#"
"TARGET_32BIT
&& GET_CODE (operands[2]) == CONST_INT
&& !const_ok_for_op (INTVAL (operands[2]), PLUS)
&& (reload_completed || !arm_eliminable_register (operands[1]))"
[(clobber (const_int 0))]
"
arm_split_constant (PLUS, SImode, curr_insn,
INTVAL (operands[2]), operands[0],
operands[1], 0);
DONE;
"
[(set_attr "length" "2,4,4,4,4,4,2,4,4,4,4,16")
(set_attr "predicable" "yes")
(set_attr "arch" "t2,*,*,*,t2,t2,t2,*,*,t2,t2,*")]
)
I saw that all the short's are handled in the thumb2.md (thumb2_addsi_short)
and the trunk has also one 2 byte length entry in the arm_addsi3. I will check
that one.
Sorry again!
