http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55623



Andrew Pinski <pinskia at gcc dot gnu.org> changed:



           What    |Removed                     |Added

----------------------------------------------------------------------------

             Target|                            |arm*-*-*, aarch64-*-*

             Status|UNCONFIRMED                 |NEW

           Keywords|                            |missed-optimization

   Last reconfirmed|                            |2012-12-09

          Component|tree-optimization           |middle-end

     Ever Confirmed|0                           |1



--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> 2012-12-09 
10:48:06 UTC ---

This is an ARM (both arm32 and arm64) specific issue due to the shifts being

"free".  If you look at the mips assembly, it looks good for a dual issue

processor as it is scheduled as an add followed by a shift.



I think the issue is reassocdoes not know that shifts are free on arm.

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