http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55247
Vladimir Makarov <vmakarov at redhat dot com> changed:
What |Removed |Added
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CC| |ubizjak at gmail dot com
--- Comment #2 from Vladimir Makarov <vmakarov at redhat dot com> 2012-11-09
19:42:30 UTC ---
Here is the insn in question:
(insn 26 25 27 2 (set (reg:TI 115 [orig:100 *defsym_17 ] [100])
(mem:TI (zero_extend:DI (reg:SI 98)) [7 *defsym_17+0 S16 A32])) h.i:54
61 {*movti_internal_rex64}
As I understand the first alternative has ! to strongly encourage to use SSE
instead of GENERAL registers.
(define_insn "*movti_internal_rex64"
[(set (match_operand:TI 0 "nonimmediate_operand" "=!r ,o ,x,x ,m")
(match_operand:TI 1 "general_operand" "riFo,riF,C,xm,x"))]
"TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
For some reasons, the second alternative does not have !. I don't know why it
is different from the first alternative.
For reload it works as it already substituted hard register for the first
operand and in this case it rejects
the 2nd alternative.
(insn 26 25 27 2 (set (reg:TI 0 ax [orig:100 *defsym_17 ] [100])
(mem:TI (zero_extend:DI (reg:SI 2 cx [98])) [7 *defsym_17+0 S16 A32]))
h.i:54 61 {*movti_internal_rex64}
Adding ! for the second alternative (as I believe it should be) solves the
problem.
(define_insn "*movti_internal_rex64"
[(set (match_operand:TI 0 "nonimmediate_operand" "=!r ,!o ,x,x ,m")
(match_operand:TI 1 "general_operand" "riFo,riF,C,xm,x"))]
"TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
Uros, is this change ok for you? If it is ok I can commit the patch only on
Wednesday (I'll be away for a few days).
