http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54089
--- Comment #21 from Oleg Endo <olegendo at gcc dot gnu.org> 2012-09-30
18:45:56 UTC ---
I've noticed that there seems to be a problem with register allocation related
to shift insns. For example in the CSiBE set, I've seen sequences such as
mov.w .L342,r2
mov #0,r7
.align 2
.L340:
mov r7,r1
add r2,r1
shar r1
mov r1,r3 <<<
shll2 r3 <<<
mov r3,r0 <<<
mov.l @(r0,r5),r3
cmp/gt r4,r3
bf 0f
quite often. Not sure why this happens. Maybe because 'gen_shifty_op' (which
emits the shift sequence insns) is called after reload and not during the first
split pass after combine...
