http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54622
--- Comment #4 from Richard Earnshaw <rearnsha at gcc dot gnu.org> 2012-09-19 22:26:49 UTC --- The reasons for the vector problems in big-endian largely fall into two areas: 1) Neon vector elements are numbered from the LSB of the vector register in both big and little-endian modes. GCC assumes that vector elements in big-endian are numbered from the MSB. This means compensation code is needed when elements are addressed directly (for example shuffle operations). 2) Quad-words in 256-bit vectors are not pure big-endian, the DWords are swapped in order on loads. GCC can't currently cope with this in any sensible manner.
