http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54593
--- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> 2012-09-15
16:50:31 UTC ---
(In reply to comment #2)
> Interesting. So it's a conscious choice that “generic” does this?
Yes:
/* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
conflict here in between PPro/Pentium4 based chips that thread 128bit
SSE registers as single units versus K8 based chips that divide SSE
registers to two 64bit halves. This knob promotes all store destinations
to be 128bit to allow register renaming on 128bit SSE units, but usually
results in one extra microop on 64bit SSE units. Experimental results
shows that disabling this option on P4 brings over 20% SPECfp regression,
while enabling it on K8 brings roughly 2.4% regression that can be partly
masked by careful scheduling of moves. */
m_PPRO | m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_AMDFAM10 | m_BDVER |
m_GENERIC,
