http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54239
Uros Bizjak <ubizjak at gmail dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |RESOLVED
Resolution| |INVALID
--- Comment #6 from Uros Bizjak <ubizjak at gmail dot com> 2012-08-13 17:32:21
UTC ---
(In reply to comment #5)
> > BTW, why do you care about the prefetch insn? Isn't it obsoleted by the SSE
> > ISA prefetches anyway (unlike prefetchw)?
>
> Hi Jakub, as for as fam15H processors what I know is they are exactly same.
> Yes I can use -mprfchw and generate prefecthw instruction and use prefetchts
> instead of prefetch instruction.
The reason is described in the comment in i386.md:
/* Use 3dNOW prefetch in case we are asking for write prefetch not
supported by SSE counterpart or the SSE prefetch is not available
(K6 machines). Otherwise use SSE prefetch as it allows specifying
of locality. */
We are generating SSE prefetches, since they allow specification of locality.
> But there is a mention in SWOG guide of amdfam15 that their functionalities
> could change in future.
>
> (Snip)
> AMD Family 15h processors implement the PREFETCHT0, PREFETCHT1, and PREFETCHT2
> instructions in exactly the same way as the PREFETCH instruction. That is, the
> data is brought into the L1 data cache. This functionality could change in
> future implementations of the AMD Family 15h
> processor
> (Snip)
I see no problem here. For current implementations, SSE prefetches are treated
in the same way as 3dNOW prefetch. I read the quoted part as "... in the
future, F15h SSE prefetches will implement the functionality as described in
the insn mnemonic (locality)", not that they will overload the mnemonic with
some other different functionality.
"Some other different functionality" will need different mnemonic, probably
supported by cpuid flag.
So, INVALID.
