http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53559
Bug #: 53559 Summary: ICE on altivec builtins stv[l|r]x[l] Classification: Unclassified Product: gcc Version: 4.8.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target AssignedTo: unassig...@gcc.gnu.org ReportedBy: ed...@freescale.com Created attachment 27545 --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=27545 config/rs6000/altivec.md (altivec_stvlx): Change machine mode of operands. When compiling any code that uses __builtin_altivec_stvlx I get an ICE: test.c: In function ‘sc1’: test.c:7:27: internal compiler error: in copy_to_mode_reg, at explow.c:647 __builtin_altivec_stvlx (v,a,p); ^ Please submit a full bug report, with preprocessed source if appropriate. See <http://gcc.gnu.org/bugs.html> for instructions. Test case is: // -O2 -maltivec -mcpu=cell -c #include <altivec.h> typedef __vector signed char vsc; void sc1(vsc v, long a, void *p) { __builtin_altivec_stvlx (v,a,p); } Compiled with: gcc -O2 -maltivec -mcpu=cell -c test.c Target: ppc64 I traced that ICE back as far as gcc-4.4.4 (Fedora 12 running on a G5: Using built-in specs. Target: ppc64-redhat-linux Configured with: ../configure --prefix=/usr --mandir=/usr/share/man --infodir=/usr/share/info --with-bugurl=http://bugzilla.redhat.com/bugzilla --enable-bootstrap --enable-shared --enable-threads=posix --enable-checking=release --with-system-zlib --enable-__cxa_atexit --disable-libunwind-exceptions --enable-gnu-unique-object --enable-languages=c,c++,objc,obj-c++,java,fortran,ada --enable-java-awt=gtk --disable-dssi --enable-plugin --with-java-home=/usr/lib/jvm/java-1.5.0-gcj-1.5.0.0/jre --enable-libgcj-multifile --enable-java-maintainer-mode --with-ecj-jar=/usr/share/java/eclipse-ecj.jar --disable-libjava-multilib --with-ppl --with-cloog --enable-secureplt --with-long-double-128 --build=ppc64-redhat-linux --target=ppc64-redhat-linux --with-cpu=default32 Thread model: posix gcc version 4.4.4 20100630 (Red Hat 4.4.4-10) (GCC) ) I found that the RTL for the builtin is created with mode V16QI, but the RTL patterns in altivec.md are defined with mode V4SI. The patch attached was tested 3 months ago on branches 4.5, 4.6, 4.7 and on trunk (4.8) with no regressions. Please let me know if the proposed solution is the right way to fix this. I will re-test the patch and submit it for approval. Thanks, Edmar