http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52110
--- Comment #4 from dave.anglin at bell dot net 2012-02-05 21:43:41 UTC --- On 5-Feb-12, at 2:12 PM, ebotcazou at gcc dot gnu.org wrote: > --- Comment #3 from Eric Botcazou <ebotcazou at gcc dot gnu.org> > 2012-02-05 19:12:36 UTC --- >> Attached is a possible patch. On "most" PARISC machines, reads and >> writes are strongly ordered and possibly this meets the "atomic" >> requirement. > > Not entirely I think, since the object is 64-bit wide. Of course, > it's a > little annoying to discover years later that the implementation > wasn't really > correct. It would be inefficient but it would be possible to implement 64-bit atomic loads and stores using floating point double loads and stores. > So I'd leave s-taspri-hpux-dce.ads unchanged and just comment out > the second > pragma Atomic, with a ??? saying that, historically, the pragma had > been > silently accepted but actually ineffective. I'll give this a try but it will take a while to test. Dave -- John David Anglin dave.ang...@bell.net
