http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51455
--- Comment #4 from Jakub Jelinek <jakub at gcc dot gnu.org> 2011-12-07 19:30:21 UTC --- Probably time for you to read the docs. E.g. AMD 24592 pdf, in 3.1.2 says: "In general, byte and word operands are stored in the low 8 or 16 bits of GPRs without modifying their high 56 or 48 bits, respectively. Doubleword operands, however, are normally stored in the low 32 bits of GPRs and zero-extended to 64 bits." Of course movzbl insn clears all upper 56 bits of the destination register, like movzbq, but is one byte shorter.
