http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50751
--- Comment #12 from Kazumoto Kojima <kkojima at gcc dot gnu.org> 2011-10-27 22:30:39 UTC --- It seems that base_reg+index_reg addressing requires special handling in RA and the move insn like (define_insn "*movqi_m_reg_reg_store" [(set (mem:QI (plus:SI (match_operand:SI 0 "arith_reg_operand" "%z") (match_operand:SI 1 "arith_reg_operand" "r"))) (match_operand:QI 2 "arith_reg_operand" "r"))] "TARGET_SH1" "mov.b %2,@(%0,%1)" [(set_attr "type" "store")]) might be unexpected for RA.