[Bug target/50725] [4.7 regression] -O3 -mstackrealign -march=core2 generates invalid prologue code in callee procedure

[jojelino at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50725

--- Comment #3 from gee <jojelino at gmail dot com> 2011-10-14 16:26:15 UTC ---
generated prologue with pseudo-reloc.ii (wrong one)
;;
;; Full RTL generated for this function:
;;
(note 8 0 11 NOTE_INSN_DELETED)

(note 11 8 459 2 [bb 2] NOTE_INSN_BASIC_BLOCK)

(insn 459 11 9 2 (set (reg:SI 344)
        (reg:SI 2 cx)) /tmp/winsup/winsup/cygwin/pseudo-reloc.cc:333 -1
     (nil))

(insn 9 459 10 2 (set (reg/v/f:SI 248 [ u ])
        (mem/f/c/i:SI (reg/f:SI 53 virtual-incoming-args) [2 u+0 S4 A32]))
/tmp/winsup/winsup/cygwin/pseudo-reloc.cc:333 -1
     (nil))

(note 10 9 12 2 NOTE_INSN_FUNCTION_BEG)

(note 12 10 13 3 [bb 3] NOTE_INSN_BASIC_BLOCK)

(insn 13 12 14 3 (set (reg:SI 250)
        (mem/s:SI (plus:SI (reg/v/f:SI 248 [ u ])
                (const_int 128 [0x80])) [4 u_1(D)->api_major+0 S4 A32]))
/tmp/winsup/winsup/cygwin/pseudo-reloc.cc:334 -1
     (nil))

generated prologue with r.c

;;
;; Full RTL generated for this function:
;;
(note 8 0 11 NOTE_INSN_DELETED)

(note 11 8 9 2 [bb 2] NOTE_INSN_BASIC_BLOCK)

(insn 9 11 10 2 (set (reg/v/f:SI 117 [ u ])
        (mem/f/c/i:SI (reg/f:SI 53 virtual-incoming-args) [7 u+0 S4 A32]))
/tmp/winsup/winsup/cygwin/pseudo-reloc.cc:273 -1
     (expr_list:REG_EQUIV (mem/f/c/i:SI (reg/f:SI 53 virtual-incoming-args) [7
u+0 S4 A32])
        (nil)))

(note 10 9 12 2 NOTE_INSN_FUNCTION_BEG)

(note 12 10 13 3 [bb 3] NOTE_INSN_BASIC_BLOCK)

(insn 13 12 14 3 (set (reg:SI 119)
        (mem/s:SI (plus:SI (reg/v/f:SI 117 [ u ])
                (const_int 120 [0x78])) [3 u_1(D)->api_major+0 S4 A32]))
/tmp/winsup/winsup/cygwin/pseudo-reloc.cc:274 -1
     (nil))

which one set the invalid (reg:SI 2 cx) constraint??