[Bug target/50457] New: SH2A atomic functions

[philip.stearns.andtr at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50457

             Bug #: 50457
           Summary: SH2A atomic functions
    Classification: Unclassified
           Product: gcc
           Version: 4.3.5
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
        AssignedTo: unassig...@gcc.gnu.org
        ReportedBy: philip.stearns.an...@gmail.com


The SH specific atomic functions don't seem to work properly with the SH2A
processor. An example function from the gcc/config/sh/linux-atomic.asm is as
follows:

#define ATOMIC_FETCH_AND_OP(OP,N,T) \
    .global    __sync_fetch_and_##OP##_##N; \
    HIDDEN_FUNC(__sync_fetch_and_##OP##_##N); \
    .align    2; \
__sync_fetch_and_##OP##_##N:; \
    mova    1f, r0; \
    mov    r15, r1; \
    mov    #(0f-1f), r15; \ <<< SP modification
0:    mov.##T    @r4, r2; \
    OP    r2, r5; \
    mov.##T    r5, @r4; \
1:    mov    r1, r15; \ <<< SP modification
    rts; \
     mov    r2, r0; \
    ENDFUNC(__sync_fetch_and_##OP##_##N)

Functions following this style cause the application to eventually crash. I
think this may be related to the locking mechanism around the instructions
making use of an on-board MMU, since the SP is loaded with a negative value. As
the SH2A does not have an MMU this poses a problem. Replacing the SP modifying
code with direct interrupt disabling/enabling resolves the problem and the
application no longer crashes:

#define ATOMIC_FETCH_AND_OP(OP,N,T,EXT) \
    .global    __sync_fetch_and_##OP##_##N; \
    HIDDEN_FUNC(__sync_fetch_and_##OP##_##N); \
    .align    2; \
__sync_fetch_and_##OP##_##N:; \
    stc    sr, r0; \
    mov    r0, r1; \
    or    #0xf0, r0; \
    ldc    r0, sr; \ <<< interrupt disable
    mov.##T    @r4, r2; \
    OP    r2, r5; \
    mov.##T    r5, @r4; \
    ldc    r1, sr; \ <<< interrupt restore
    rts; \
     EXT    r2, r0; \
    ENDFUNC(__sync_fetch_and_##OP##_##N)