http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50107
Bug #: 50107
Summary: [IRA, i386] allocates regiters in very non-optimal way
Classification: Unclassified
Product: gcc
Version: 4.7.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: rtl-optimization
AssignedTo: unassig...@gcc.gnu.org
ReportedBy: kirill.yuk...@intel.com
Created attachment 25032
--> http://gcc.gnu.org/bugzilla/attachment.cgi?id=25032
Patch, enabling MULX insn
Hi,
I am working on enabling of new MULX instruction for GCC.
It have to relax generic unsigned mult in two ways: no falgs are clobbered, and
(the main) destination may be arbitrary 2 GPR's.
Patch is attached along with testcase.
Problem is that such relaxation leads to useless spills/fills.
Command line is:
./build-x86_64-linux/gcc/xgcc -B./build-x86_64-linux/gcc test.c -S -Ofast
Here is assembly with MULX:
test_mul_64:
.LFB0:
movq %rdi, %rdx
pushq %rbx <--------
mulx %rsi, %rbx, %rcx
addq $3, %rcx
adcq $0, %rbx
movq %rcx, %rax
movq %rcx, k2(%rip)
movq %rbx, %rdx <--------
movq %rbx, k2+8(%rip)
popq %rbx <--------
ret
You can see, that if we replace ebx usage with edx, instruction marked with
arrows will dissapear.
Maybe the problem is connected with my definition of MULX?
But it seems to me as IRA misoptimization.
BTW, r8, r9 etc. regs are caller-safe, so we may just use them without saving
to stack? Why IRA doesn't do that?
Thanks, K
