http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49641
Summary: [ARM] Wrong code for ARMv4T and stmia
Product: gcc
Version: 4.6.1
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
AssignedTo: unassig...@gcc.gnu.org
ReportedBy: sebastian.hu...@embedded-brains.de
Target: arm-rtemseabi4.11
Created attachment 24689
--> http://gcc.gnu.org/bugzilla/attachment.cgi?id=24689
Sample code.
The attached source code generates the following assembler code:
00000000 <_Watchdog_Handler_initialization>:
0: 2200 movs r2, #0
2: 4b06 ldr r3, [pc, #24] ; (1c
<_Watchdog_Handler_initialization+0x1c>)
4: 601a str r2, [r3, #0]
6: 4b06 ldr r3, [pc, #24] ; (20
<_Watchdog_Handler_initialization+0x20>)
8: 601a str r2, [r3, #0]
a: 4b06 ldr r3, [pc, #24] ; (24
<_Watchdog_Handler_initialization+0x24>)
c: 601a str r2, [r3, #0]
e: 4b06 ldr r3, [pc, #24] ; (28
<_Watchdog_Handler_initialization+0x28>)
10: 1d19 adds r1, r3, #4
12: c30e stmia r3!, {r1, r2, r3}
14: 4b05 ldr r3, [pc, #20] ; (2c
<_Watchdog_Handler_initialization+0x2c>)
16: 1d19 adds r1, r3, #4
18: c30e stmia r3!, {r1, r2, r3}
1a: 4770 bx lr
In particular it generates: stmia r3!, {r1, r2, r3}
This instruction leads to UNPREDICTABLE behavior. According to "ARM
Architecture Reference Manual, Issue I" we have in section "A7.1.57 STMIA",
"Operand restrictions":
"If <Rn> is specified in <registers>:
o If <Rn> is the lowest-numbered register specified in <registers>, the
original value of <Rn> is stored.
o Otherwise, the stored value of <Rn> is UNPREDICTABLE."
Since r3 is not the lowest-numbered register specified in {r1, r2, r3} the
stored value of r3 is UNPREDICTABLE.
