[Bug rtl-optimization/48596] [4.7 Regression] [SH] unable to find a register to spill in class 'FPUL_REGS'

[kkojima at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48596

Kazumoto Kojima <kkojima at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|                            |ice-on-valid-code
             Target|                            |sh-*-*
      Known to work|                            |4.6.0
      Known to fail|                            |4.7.0

--- Comment #1 from Kazumoto Kojima <kkojima at gcc dot gnu.org> 2011-04-13 
22:47:25 UTC ---
It started to fail between revisions 171582 and 171649.

.ira dump says

Spilling for insn 105.
Using reg 150 for reload 0
reload failure for reload 3

Reloads for insn # 105
Reload 0: FPUL_REGS, RELOAD_FOR_OUTPUT_ADDRESS (opnum = 0), can't combine,
secondary_reload_p
Reload 1: reload_in (SI) = (reg/f:SI 78 fr14 [orig:242 D.2027 ] [242])
    GENERAL_REGS, RELOAD_FOR_OUTPUT_ADDRESS (opnum = 0)
    reload_in_reg: (reg/f:SI 78 fr14 [orig:242 D.2027 ] [242])
    secondary_in_reload = 0
Reload 2: GENERAL_REGS, RELOAD_FOR_OUTPUT_ADDRESS (opnum = 0), can't combine,
secondary_reload_p
Reload 3: reload_out (SI) = (mem:SI (reg/f:SI 78 fr14 [orig:242 D.2027 ] [242])
[0 MEM[(struct Info *)D.2027_55]+0 S4 A32])
    FPUL_REGS, RELOAD_FOR_OUTPUT (opnum = 0)
    reload_out_reg: (reg:SI 264)
    secondary_out_reload = 2

It looks odd to choose floating point register fr14 for a memory address.